XR16C872 Datasheet, PDF (29/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

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XR16C872
LSR BIT-5:
This bit is the Transmit Holding Register Empty indica-
tor. This bit indicates that the UART is ready to accept
a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to CPU when the
THR interrupt enable is set. The THR bit is set to a logic
1 when a character is transferred from the transmit
holding register into the transmitter shift register. The bit
is reset to logic 0 concurrently with the loading of the
transmitter holding register by the CPU. In the FIFO
mode this bit is set when the transmit FIFO is empty;
it is cleared when at least 1 byte is written to the transmit
FIFO.
LSR BIT-6:
This bit is the Transmit Empty indicator. This bit is set
to a logic 1 whenever the transmit holding register and
the transmit shift register are both empty. It is reset to
logic 0 whenever either the THR or TSR contains a data
character. In the FIFO mode this bit is set to one
whenever the transmit FIFO and transmit shift register
are both empty.
LSR BIT-7:
Logic 0 = No Error (normal default condition)
Logic 1 = There is at least one parity error, framing error
or break indication is in the current FIFO data. This bit
is cleared when LSR register is read.
When the LSR is read, bit 2,3 and 4 reflects the error
bits of the character on top of the RX FIFO, next
character to be read in RHR. Therefore, errors in a
character are identified by reading the LSR and then
reading the data character in RHR.
Modem Status Register (MSR)
This register provides the current state of the control
interface signals from the modem, or other peripheral
device that the UART A or B is connected. Four bits of
this register are used to indicate the changed informa-
tion. These bits are set to a logic 1 whenever a control
input from the modem changes state. These bits are set
to a logic 0 whenever the CPU reads this register.
MSR BIT-0:
Logic 0 = No CTS# Change (normal default condition)
Logic 1 = The CTS# input to the uart has changed state
since the last time it was read. A modem Status Interrupt
will be generated.
MSR BIT-1:
Logic 0 = No DSR# Change (normal default condition)
Logic 1 = The DSR# input to the uart has changed state
since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-2:
Logic 0 = No RI# Change (normal default condition)
Logic 1 = The RI# input to the UART has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No CD# Change (normal default condition)
Logic 1 = Indicates that the CD# input to the has
changed state since the last time it was read. A modem
Status Interrupt will be generated.
MSR BIT-4:
CTS# functions as hardware flow control signal input if
it is enabled via EFR bit-7. The transmit holding register
flow control is enabled/disabled by MSR bit-4. Flow
control (when enabled) allows suspending and resum-
ing data transmissions based on the external modem
CTS# signal. A logic 1 at the CTS# pin will suspend
transmissions as soon as current character has fin-
ished transmission.
Normally MSR bit-4 bit is the compliment of the CTS#
input. However in the loop-back mode, this bit is
equivalent to the RTS bit in the MCR register.
Rev. 1.00
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