XR16C872 Datasheet, PDF (32/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
FCTR BIT-6:
Scratch Pad Register (SPR) or EMSR select.
0 = Scratch Pad Register (SPR) is selected as general
read and write register. 16C550 compatible mode.
1 = FIFO count register, Enhanced Mode Select Reg-
ister (EMSR). Number of characters in transmit or
receive holding register can be read via Scratch Pad
Register when this bit is set. Enhanced Mode is selected
when it is written into it.
count when it is read.
Example to read the number of character count in TX or
RX FIFO.
In the Initialization routine:
set LCR to 0xBF
; point to enhanced registers
set FCTR bit-6 to logic 1 ; swap SPR to be FIFO counters and
; point to EMSR register
set LCR to operating parameters
FCTR BIT-7:
Programmable trigger register select.
0 = Receiver programmable trigger level register (TRG)
is selected.
1 = Transmitter programmable trigger level register
(TRG) is selected.
TRIGGER LEVEL/FIFO COUNT REGISTER (TRG)
This register is only accessible when LCR is set to 0xBF.
This register provides the user programmable transmit
or receive trigger level from byte 0 to 128 (0xFF), and
reading the number of data bytes in the transmit or
receive FIFO.
TRG BIT 0-7: Write only.
This register sets the user programmable transmit or
receive FIFO trigger levels. FCTR bit-7 must be set and
point to the transmitter or receiver prior programming the
trigger level.
TRG BIT 0-7: Read only.
Transmit / receive FIFO count. Number of characters in
transmit or receive FIFO can be read via this register.
FCTR bit-7 must be set and point to the transmitter or
receiver prior reading the FIFO count.
- in RX routine -
set EMSR bit-0 to logic 0
read SPR
or
- in TX routine -
set EMSR bit-0 to logic 1
read SPR
; set to read RX FIFO count
; obtain RX FIFO count
; read TX FIFO count
; obtain TX FIFO Count
EMSR BIT-1: Write only
0 = Normal.
1 = Alternate receive - transmit FIFO count. When
EMSR Bit-0=1 and EMSR Bit=1, Scratch Pad Register
is used to provide the receive - transmit FIFO count
when it is read every alternate read cycle. The TRG Bit-
7 will provide FIFO count mode information, TRG Bit-
7=0 receive mode, TRG Bit-7=1 transmit mode.
EMSR BIT-2: Write only
This bit is not available in the 872.
EMSR BIT4 and 5 - Write only
These bits select the RTS flow control hysteresis and are
associated with FCTR bit 0 and 1. The RTS hysteresis
is reference to the RX FIFO trigger level. Below table
show the 16 selectable hysteresis.
ENHANCED MODE SELECT REGISTER (EMSR)
This register is only accessible when LCR is set to 0xBF
and FCTR Bit-6 is set to logic 1.
EMSR BIT-0: Write only
0 = Receive FIFO count register. The Scratch Pad
Register (SPR) is used to provide the receive FIFO
count when it is read.
1 = Transmit FIFO count register. The Scratch Pad
Register (SPR) is used to provide the transmit FIFO
Rev. 1.00
32
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