XR16C872 Datasheet, PDF (30/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
MSR BIT-5:
DSR (active high, logical 1). Normally this bit is the compliment of the DSR# input pin. In the loop-back mode, this
bit is the complement to the DTR bit in the MCR register.
MSR BIT-6:
RI (active high, logical 1). Normally this bit is the compliment of the RI# input. In the loop-back mode this bit is
equivalent to the OP1# bit in the MCR register.
MSR BIT-7:
CD (active high, logical 1). Normally this bit is the compliment of the CD# input. In the loop-back mode this bit is
equivalent to the OP2# bit in the MCR register.
Scratch Pad Register (SPR)
The UART A or B has a temporary data register to store 8 bits of user information. The register content is set to 0xFF
upon power up or a hardware reset. This register is alternately used as TX or RX FIFO counter register, when FCTR
bit-6=1 with EMSR bit-0 defining for TXCNT or RXCNT.
Enhanced Feature Register (EFR)
This register is only accesible when LCR is set to 0xBF. Enhanced feature functions in the 16C550 base register
set area are enabled using this register bit-4. These are IER bits 4-7, ISR & FCR bits 4-5, and MCR bits 5-7.
Bits-0 through 3 provide single or dual character software flow control selection. When the Xon1 and Xon2 and/or Xoff1
and Xoff2 modes are selected (see Table 5), the double 8-bit words are concatenated into two sequential characters.
EFR BIT 0-3: (logic 0 or cleared is the default condition)
Combinations of software flow control can be selected by programming these bits.
Cont-3 Cont-2 Cont-1 Cont-0 TX, RX software flow controls
0
0
X
X
No transmit flow control
1
0
X
X
Transmit Xon1/Xoff1
0
1
X
X
Transmit Xon2/Xoff2
1
1
X
X
Transmit Xon1 and Xon2/Xoff1 and Xoff2
X
X
0
0
No receive flow control
X
X
1
0
Receiver compares Xon1/Xoff1
X
X
0
1
Receiver compares Xon2/Xoff2
1
0
1
1
Transmit Xon1/ Xoff1.
Receiver compares Xon1 and Xon2,
Xoff1 and Xoff2
0
1
1
1
Transmit Xon2/Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
1
1
1
1
Transmit Xon1 and Xon2/Xoff1 and Xoff2
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
0
0
1
1
No transmit flow control
Receiver compares Xon1 and Xon2/Xoff1 and Xoff2
Rev. 1.00
Table 5, Software Flow Control Registers
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