XR16C872 Datasheet, PDF (20/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the internal registers. UART A and B has same
register set independently control. The assigned bit functions are defined in the following paragraphs.
UART INTERNAL REGISTERS
A2 A1 A0
Register
[Default]
Note *3
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
Basic Registers are accessible when LCR bit-7 is set to logic 0. (Shaded bits are enabled by EFR bit-4)
000
RHR [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
000
001
010
010
THR [XX]
IER [00]
FCR [00]
ISR [01]
bit-7
bit-6
bit-5
bit-4
bit-3
1111111122222222_in33333333_Cte44444444_T0r55555555_Sr/u66666666_#p77777777_t888888881111111122222222_{in33333333Rt44444444eT055555555rSr/66666666u#p77777777t}88888888
RCVR
trigger
(MSB)
0/
FIFO’s
enabled
RCVR
trigger
(LSB)
0/
FIFO’s
enabled
11111111111111111111111_i22222222222222222222222_n(RtCrtM33333333333333333333333_X0eiTgT/0044444444444444444444444_oTSrSgSr//X55555555555555555555555_fBue##f66666666666666666666666_{rp), t}77777777777777777777777
1111111111111111111111122222222222222222222222_tS(m33333333333333333333333_r0LDiXlg44444444444444444444444_{/0o0eSTeogd//e}55555555555555555555555_BXftfe.ep66666666666666666666666_)r 7777777777777777777777788888888
modem
status
interrupt
DMA
mode
select
int
priority
bit-2
bit-2
receive
line
status
interrupt
XMIT
FIFO
reset
int
priority
bit-1
bit-1
transmit
holding
register
RCVR
FIFO
reset
int
priority
bit-0
bit-0
receive
holding
register
FIFO
enable
int
status
011
100
LCR [00]
MCR [00]
divisor
set
set
latch
break
parity
111111122222223333333^esCne4444444_laol5555555_ebc6666666_clket77777778888888111111122222223333333_{eI4444444nR0a5555555R/b6666666Tle77777778888888} 1111111_X2222222_o3333333_n04444444_-/A5555555_n6666666_y77777778888888
even
parity
loop
back
parity
stop
enable
bits
(OP2#) (OP1#)
word
length
bit-1
RTS#
word
length
bit-0
DTR#
101
LSR [60]
0/
FIFO
error
trans.
trans.
break
shift reg. holding interrupt
empty reg. empty
framing
error
parity
error
overrun
error
receive
data
ready
1 1 0 MSR [00]
CD#
1 1 1 ₁₁₁₁SF_{2222IP3333FR4444O5555}[CF_{6666oF7777u]8888not9999}r 0000 bit-7
RI#
bit-6
DSR#
CTS#
bit-5
bit-4
delta
CD#
bit-3
delta
RI#
bit-2
delta
DSR#
bit-1
delta
CTS#
bit-0
Baud Rate Generator Registers are accessible only when LCR bit-7 is set to a logic 1.
000
DLL [XX]
bit-7
bit-6
bit-5
bit-4
bit-3
bit-2
bit-1
bit-0
001
DLM [XX]
bit-15
bit-14
bit-13
bit-12
bit-11
bit-10
bit-9
bit-8
Rev. 1.00
Visit Exar Web Site at www.exar.com
20