XR16C872 Datasheet, PDF (34/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
DISCONTINUED
1284 Controller
The bi-directional parallel data port controller is compatible to IEEE Standard 1284 interface. The 1284 interface
can be programmed as a standard printer port or bi-directional parallel port for high speed data transfer systems.
The 1284 interface provides 1284 Level II electrical interface, needing no external transceivers to interface to the
parallel port cable. Hence, it can connect directly to a printer or a high speed bi-directional parallel device. The 1284
controller supports the following modes of operation.
• Standard Centronics interface, forward only
• Bi-directional Centronics.
• Parallel port with data FIFO.
• ECP, Extended Capabilities Port, and with 16 byte data FIFO in Forward and Reverse modes, supports
Run Length Encoded (RLE) de-compression in the reverse mode, however, no compression is sup-
ported in the forward mode, and Direct Memory Access transfer capability.
• EPP, Enhanced Parallel Port.
On a reset, the device defaults to compatible mode which is the standard PC Centronics printer mode in PC
computers. The EPP, and ECP modes can only be activated by programming the Extended Control Register (ECR),
this requires address bit A10=1, which is outside the normal parallel port address in the ISA I/O space. The internal
timing is designed to operate from a 22.1184 MHz clock which is supplied from an external source on pin XTAL1
or by the built-in oscillator circuit with an appropriate crystal.
Optional capabilities of the ECP specification are set as follows:
• ECP defined interrupts are pulsed, low true (Centronics ACK# is non-pulsed, low true).
• PWord size is forced to 1 byte.
• There is 1 byte in the transmitter that does not affect the FIFO full bit (ECP modes).
• RLE compression is not supported in hardware.
• IRQ channel is selectable as 5, 7, or 9.
• DMA channel is selectable as 3
• FIFO THRESHOLD is set at 8 (used only for non-DMA access to the FIFO).
PORT
ADDRESS Read/Write MODE FUNCTION
DATA
ECP-AFIFO
DSR
DCR
EPP-APort
EPP-DPort
C-FIFO
ECP-DFIFO
T-FIFO
Cnfg-A
Cnfg-B
ECR
000
000
001
002
003
004-007
400
400
400
400
401
402
R/W
W
R
R/W
R/W
R/W
W
R/W
R/W
R
R-R/W
R/W
000
Data port
011
ECP FIFO (Address)
All
Status Register
All
Control Register
100
EPP Port (Address)
100
EPP Port (Data)
010
Parallel Port Data FIFO
011
ECP FIFO (Data)
110
Test FIFO
111
Configuration Register A
111
Configuration Register B
All
Extended Control Register
Rev. 1.00
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