XR16C872 Datasheet, PDF (18/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

XR16C872
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The generator divides the input 16X clock by any divisor
from 1 to 2¹⁶ -1. The UART divides the input clock by 16.
Further division of this 16X clock provides two table rates
to support low and high data rate applications using the
same system design. The two rate tables are selectable
through the internal register, MCR bit-7. Setting MCR
bit-7 to logic 1 provides an additional divide by 4
whereas, setting MCR bit-7 to logic 0 only divides by 1.
(See Table 3 and Figure 6). The frequency of the
internal sampling rate is exactly 16X (16 times) of the
selected baud rate. Customized Baud Rates can be
achieved by selecting the proper divisor values for the
MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers DLM
(MSB) and DLL (LSB) provides the user capability for
selecting the desired serial baud rate. Table 3 shows the
two selectable baud rate tables available with the 7.3728
MHz clock. The output data rate tolerance is determined
by the frequency accuracy of the 22.1184MHz crystal
or external clock.
DMA Operation
The FIFO trigger level provides additional flexibility to the
user for data block transfer operation. LSR bits 5-6
provide an indication when the transmitter is empty or
has an empty location(s). The user can optionally
operate the transmit and receive FIFOs in the DMA
mode (FCR bit-3). When transmit and receive FIFOs
are enabled and the DMA mode is deactivated (DMA
Mode “0”), the UART activates the interrupt output pin
for each data transmit or receive operation. When DMA
mode is activated (DMA Mode “1”), the user takes the
advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by
the preset trigger level. In this mode, the UART asserts
the interrupt output pin when characters in the transmit
FIFOs are below the transmit trigger level, or the number
of characters in the receive FIFOs are above the receive
trigger level. Transmit or receive DMA operation is
selected by EMSR register bit 2.
Sleep Mode
The UARTs are designed to operate with low power
consumption. A sleep mode is included to further
reduce power consumption when the chip is not being
used. The operating parameters are maintained while in
sleep. With EFR bit-4 and IER bit-4 enabled (set to logic
1), the UART enters the sleep mode when no interrupt
is pending and no activities on the modem port. If an
external clock is supplied to the UART, you may want to
stop it. The UART resumes normal operation when a RX
character’s start bit is detected, a change of state on any
of the modem input pins RX, RI#, CTS#, DSR#, CD#,
or transmit data is loaded into the FIFO by the user. It
typically takes 30us for the crystal oscillator to restart
from sleep mode depending on the crystal properties.
This delay must be taken into consideration during
design as receive character(s) may be lost. The number
of characters lost depends on the operating data rate,
more at higher data rate. If the sleep mode is enabled
and the UART is awakened by one of the conditions
described above, it will return to the sleep mode auto-
matically after the last character is transmitted or read
by the user and no interrupt pending. The chip will not
enter sleep mode whiles an interrupt(s) is still pending
and the oscillator would still be running. The UART stays
in the sleep mode of operation until it is disabled by
setting IER bit-4 to logic 0.
Example of Sleep mode enable during initialization:
Write LCR with 0xBF
Set EFR bit-4 to logic 1
Write LCR with Op.value
Set IER bit-4 to logic 1
; access to EFR registers
; enable non-550 functions
; in IER, EFR and MCR registers
; point to basic registers
; set sleep mode
; service all pending interrupts
; no modem port activity
; enters sleep mode and stop
; the oscillator
For lowest sleep current the following pins should idle at logic 1
state: RX A/B should be at logic 1 and data bus should be pull-
down with ~47K resistors if the controller puts the data bus in
tri-state condition. No input pins should be left floating.
Loopback Mode
The internal loopback capability allows on board diag-
nostics. In this mode, the normal modem interface pins
are disconnected and re-configured for loopback inter-
nally. MSR bits 4-7 are also disconnected. However,
MCR register bits 0-3 can be used for controlling
loopback diagnostic testing. In this mode, OP1 and OP2
in the MCR register (bits 0-1) control the modem RI# and
CD# inputs respectively. MCR signals DTR# and RTS#
(bits 0-1) are used to control the modem CTS# and
Rev. 1.00
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