XR16C872 Datasheet, PDF (25/60 Pages) Exar Corporation – DUAL UART WITH 1284 PARALLEL PORT AND PLUG-AND-PLAY CONTROLLER

DISCONTINUED
XR16C872
TRIGGER TABLE-D (Transmit)
BIT-5 BIT-4
FIFO trigger level
X
X
User programmable
trigger levels
TRIGGER TABLE-D (Receive)
BIT-7 BIT-6
FIFO trigger level
X
X
User programmable
trigger levels
FCR BIT 6-7: (logic 0 or cleared is the default condition,
RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The interrupt will trigger again
when RX data got unloaded below the threshold and
incoming data fill it back up to the trigger level. The FCTR
Bits 4-5 selects one of the following table.
TRIGGER TABLE-A (Receive)
“Default setting after reset, ST16C550 mode”
BIT-7 BIT-6
FIFO trigger level
0
0
1
0
1
4
1
0
8
1
1
14
An example to program the FIFO trigger level:
write LCR with 0xBF
; point to enhanced registers
set FCTR bit4-5 to logic 1 ; select trigger Table-D
set FCTR bit-7 to logic 0 ; program RX FIFO trigger level
write TRG with 0x60
; set your RX trigger level to 96
set FCTR bit-7 to logic 1 ; program TX FIFO trigger level
write TRG with 0x08
; set your TX trigger level to 8
write LCR with 0x03
; set operating parameters
Receive data ready interrupt will activates when RX FIFO fills up to
96 data bytes while the transmit empty interrupt gets set when
data is empty to 8 bytes.
TRIGGER TABLE-B (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
24
1
1
28
TRIGGER TABLE-C (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
56
1
1
60
Rev. 1.00
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