SAP5SD-A-G1-T Datasheet, PDF (54/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
In Master/Repeater Mode the SAP5 provides an AS-i power-fail detector. It consists of a comparator directly
connected to the LTGP pin which generates a logic signal in case the voltage at the LTGP pin drops below
V_APF (refer to Table 39). A subsequent digital signal processing of the comparator output signal is performed
as follows:
 An anti-bouncing filter removes each signal states shorter than 6s. This is to eliminate the influence
of AS-i telegrams which are added onto the AS-i DC voltage.
 An additional anti-bouncing filter with different filter times for activation and deactivation of the power-
fail signal removes short power-fail pulses.
 The AS-i power-fail signal is provided directly active HIGH as signal APF.
 Additionally, in Master Mode, the AS-i power-fail signal modulates the RX_DAT signal, whereas the
active state is signaled by logic HIGH level.
Table 39: Master/Repeater Mode Parameter
Symbol
t_loopback
V_APF
t_{APF_RX_DAT}
t_{APF_ON_RX_DAT}
t_{APF_APF}
t_{HOLD_APF}
t_{APF_OFF}
t_BREAK
Parameter
Min Max Unit
Loopback time in Master Mode
4.9 6.5 s
AS-i Power Fail voltage threshold
21. 23. V
55
minimum activation time for signaling of AS-i Power 640 704 s
Fail by use of the RX_DAT signal
release time of the AS-i Power Fail state within the 64
s
RX_DAT signal
minimum activation time for signaling of AS-i Power 704 768 s
Fail by use of the APF signal
AS-i Power Fail hold time
64
s
delay time after return of the AS-i Power
64 128 s
break time in case of an erroneous AS-i signal
9 15 s
Note
1
2
2
2
1 _{Loopback time is the time difference between an edge in the MAN code of signal TX_DAT and the}
corresponding edge in the Manchester-code of the signal RX_DAT. The voltage trigger level for measurement
of the edge time is defined by V_U5R/2. The actual loopback time may be adjusted by programming the
ID_Code_Extension_2 EEPROM register as described in Table 38.
2 _{In Master Mode, the AS-i Power Fail state is already signaled by the RX_DAT signal as soon as the power}
fail condition is true for a time more than t_{APF_RX_DAT.} However, in order to start the APF minimum hold state
(t_{HOLD_APF}), the power fail condition must remain true for another time period defined by t_{APF_ON_RX_DAT}.
Otherwise, the RX_DAT signal returns to its idle state (logic LOW) immediately.
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
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