SAP5SD-A-G1-T Datasheet, PDF (30/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
4.3. DC Characteristics – Digital Inputs
The following pins contain digital high voltage input stages:
-
Input-only pin:
-
I/O pins:
-
3-level I/O pins:
PFAULT
P1, P3, D1, D3, DSTBn, PSTBn ¹, LED1 ¹
P0, P2, D0, D2 ³
Table 16: DC Characteristics of digital high voltage input pins
Symbol Parameter
Min Max Unit
Note
V_OFL Voltage range for input ”offset_low” level
0
1.0
V
3,4
V_OFH Voltage range for input ”offset_high” level
1.6 V_UOUT
V
3,4
V_IL2
Voltage range for input ”low” level
0
2.5
V
4
V_IH
Voltage range for input ”high” level
I_IL
Current range for input ”low” level
I_IH
Current range for input ”high” level
C_DL
Capacitance at pin DSTBn
3.5 V_UOUT
V
-12
-3
µA
-10
10
µA
10
pF
V_IN = 1V ²
V₀  V_U5R
5
1 _{PSTBn and LED1 are inputs for test purposes only.}
2 _{The pull-up current is driven by a current source connected to U5R. It stays almost constant for input}
voltages ranging from 0 to 3.8V.
3 _{Pins P0, P2, D0 and D2 are used as 3-level inputs - i.e. inputs with offset detection - in Safety Mode only,}
configuration beyond depends on the slave profile (refer to Table 26 on page 40)
4 _{The 3-level input pads contain independent comparators for the detection of regular input data level and}
offset. Refer to Figure 12 on page 50 for constraints to the externally applied voltages in Safety Mode.
5 _{The internal pull-up current is sufficient to avoid accidental triggering of an IC reset if the DSTBn pin remains}
unconnected. For external loads at DSTBn a sufficient pull up resistor is required to ensure V_IH  3.5V in less
than 90ms after the beginning of a DSTBn = Low pulse.
4.4. DC Characteristics – Digital Outputs
The following pins contain digital high voltage open drain output stages:
-
Output-only pin:
-
I/O pins:
LED2
D0 … D3, P0 … P3, DSTBn, PSTBn¹, LED1¹
Table 17: DC Characteristics of digital high voltage output pins
Symbol Parameter
Min Max. Unit
Note
V_OL1 Voltage range for output ”low” level
V_OL2 Voltage range for output ”low” level
I_OH
Output leakage current
1 _{PSTBn and LED1 are inputs for test purposes only.}
0
1
V I_OL1 = 10mA
0
0.4
V I_OL2 = 2mA
-10
10
µA V_0H  V_U5R
A slew rate limitation is provided to each digital high voltage output driver which limits the rise and fall times
for both High/Low and Low/High transitions to 40…50ns.
NOTE: The rise time for a Low/High transition is mainly influenced by the external pull-up resistor.
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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