SAP5SD-A-G1-T Datasheet, PDF (15/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
UART
/ ^{E²PROM write access and other I/O operations of the Main State Machine are supported}
MAIN STATE ^{in Slave Mode only (see description of general IC operational modes below). In Master}
MACHINE
/ ^{Mode the IC is basically equivalent to a physical layer transceiver.}
EEPROM
If Slave Mode is activated, the UART demodulates the received telegrams, verifies
telegram syntax and timing and controls a register interface to the Main State Machine.
After reception of a correct telegram, the UART generates appropriate Receive Strobe
signals, that tell the Main State Machine to start further processing. The Main State
Machine decodes the telegram information and starts respective I/O processes or
E²PROM access. A second register interface is used to send data back to the UART for
construction of a telegram response. The UART modulates the response data into a
Manchester-II-coded bit stream that is used to control the TRANSMITTER unit.
ELECTRONIC The electronic inductor is basically a gyrator circuit. It provides an inductive behavior
INDUCTOR
between the IC pins LTGP and UOUT while the inductance is controlled by the capacitor
on pin CDC. The inductor decouples the power regulator of the IC as well as the external
load circuit from the AS-i bus and hence prevents cross talk or switching noise from
disturbing the telegram communication on the bus.
The AS-i Complete Specification describes the input impedance behavior of a slave
module by an equivalent circuit that consists of R, L and C in parallel. For example, a
slave module in Extended Address Mode shall have R > 13.5 kOhm, L > 13.5 mH and C <
50pF. The electronic inductor of the SAP5 delivers values that are well within the required
ranges for output currents up to 55mA (Uin>24V). More detailed parameters can be found
in chapter 4.1.
The electronic inductor requires an external capacitor of 10µF at pin UOUT for stability.
POWER
The power supply block consists of a bandgap referenced 5V-regulator as well as other
SUPPLY
reverence voltage and bias current generators for internal use. The 5V regulator requires
an external capacitor at pin U5R of at least 100nF for stability. It can source up to 4mA for
external use, however the power dissipation and the resulting device heating become a
major concern, if too much current is drawn from the regulator. See chapter 4.1.
OSCILLATOR / The oscillator supports direct connection of 5.33 MHz or 16.000 MHz crystals with a
PLL
dedicated load capacity of 12pF and parasitic pin capacities of up to 8pF. The IC
automatically detects the oscillation frequency of the connected crystal and controls the
internal clock generator circuit accordingly.
After power-on reset the IC is set to 16.000 MHz operation by default. After about 200µs it
will either switch to 5.333 MHz operation or remain in the 16.000 MHz mode. The
frequency detection is active until the first AS-i telegram was successfully received in
order to make sure the IC found the correct clock frequency setting. The detection result
is locked thereafter to increase resistance against burst or other interferences.
The oscillator unit also contains a clock watch dog circuit that can generate an
unconditioned IC reset if there was no clock oscillation for more than about 20µs. This is
to prevent the IC from unpredicted behavior if no clock signal is available anymore.
THERMAL
The IC is self protected against thermal overload. If the silicon die temperature rises
PROTECTION above around 140°C for more than 2 seconds, the IC detects thermal overheating,
switches off the electronic inductor, performs an IC reset and sets all analog blocks to
power down mode. The 5V-regulator is of course also turned off in this state, however,
there will still remain a voltage of about 3 … 3.5V available at U5R that is derived from the
internal start circuitry. If the overheat condition is left the IC resumes operation and
performs an initialization.
POWER FAIL The Power Fail Detector observes the voltage at the AS-i-line. It signals at pin
DETECTOR
PSTBn/APF when the voltage drops below about 22.5V. Active in Master Mode only.
INPUT STAGE All digital inputs, except of the oscillator pins, have high voltage capabilities and pull-up
features. For more details see chapters 1.7, 4.3, 4.7, and 4.8.
OUTPUT
All digital output stages, except of the oscillator pins, have high voltage capabilities and
STAGE
are implemented as NMOS open drain buffers. Each pin can sink up to 10mA of current.
See chapter 4.4.
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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