SAP5SD-A-G1-T Datasheet, PDF (37/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
The Data I/O operation is repeated together with the I/O cycle of the other Synchronous Mode slaves
in the network at the common trigger event. By that, the particular slave has fully reached the
Synchronous Mode.
If the P2 output register changes from ‘0’ to ‘1’ the Synchronous Data IO Mode gets deactivated and
disabled immediately. In case a synchronous data I/O event was already scheduled but not yet
processed (armed but no fired) before the Synchronous Data I/O Mode became deactivated, the
associated data output value gets lost.
Reactivation of the Synchronous Data I/O Mode occurs in same manner as described above if P2
changes back to ‘0’.
 To avoid a general suppression of Data I/O in the special case that a slave in Synchronous Mode
receives DEXG calls only to its own address (i.e. employment of a handheld programming device),
the Synchronous Mode becomes deactivated, once the SAP5 receives three consecutive DEXG calls
to its own slave address. The IC resumes to Synchronous Mode operation after it observed a DEXG
call to a different slave address then its own. The reactivation of the Synchronous Mode is handled
likewise for the first DEXG call after activation of the Data Port or after activation of the Synchronous
Data I/O Mode by P2 changing to ‘0’ (see description above).
If any of the data ports D0..D3 is configured as pure output (named OUT in Table 25), the SAP5 returns the
output data that was received from the master immediately back in its slave response. Since there is no input
function available at such port, the return value is independent from a possible Synchronous Mode operation.
Running in Synchronous Mode, the SAP5 generates the Data Strobe (DSTBn) signal as well, whereas the
timing of input sampling and output buffering exactly corresponds to the regular operation (refer to Figure 7
and Table 21).
4.8.4. Support of 4I/4O Signaling in Extended Address Mode
In Extended Address Mode the information bit I3 of the AS-i master telegram is used to distinguish between A-
and B-slaves that operate in parallel at the same AS-i slave address. For more detailed information refer to [1]
AS-i Complete Specification.
Besides the benefit of an increased address range, the cycle time per slave is increased in Extended Address
Mode from 5 ms to 10 ms and the useable output data is reduced from 4 to 3 bits. Because of the later,
Extended Address Mode slaves can usually control a maximum of 3 data outputs only. The input data
transmission is not effected since the slave response still carries 4 data information bits in Extended Address
Mode.
Additionally, the SAP5 supports applications that require 4 bit wide output data in Extended Address Mode,
but can tolerate further increased cycle times (i.e. push buttons and pilot lights). Such applications shall be
directly characterized by a new Slave Profile 7.A.x.7 that is to be defined in the AS-i Complete Specification.
If the IC is operated in Extended Address Mode and the Ext_Addr_4I/4O_Mode flag is set (=’1’) in the
E²PROM (refer to Table 9) it treats information bit I2 as selector for two 2-bit wide data output banks:
o Bank_1 = D0/D1
o Bank_2 = D2/D3.
A master shall consecutively transmit data to Bank_1 and Bank_2, toggling the information bit I2 in the
respective master calls. However, the SAP5 triggers a data output event (modification of the Data Output
Ports and generation of Data Strobe) as follows:
o If the Parallel_Out_4I/4O flag is set (=’1’) in the E²PROM (refer toTable 9) the SAP5 triggers a
data output event only if information bit I2 is equal to ‘0’. By that, new output data is issued at
the Data Port synchronously for both banks at the same time.
o If the Parallel_Out_4I/4O flag is not set (=’0’) the SAP5 triggers a data output event at every
cycle. However, depending on the information bit I2 only one bank of the Data Port gets
refreshed.
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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