SAP5SD-A-G1-T Datasheet, PDF (42/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
4.12. Oscillator Pins OSC1, OSC2
Table 28: Oscillator pin parameters
Symbol
Parameter
Min Max Unit Note
V_{OSC_IN}
Input voltage range
-0.3 V_U5R V
C_OSC
External parasitic capacitor at oscillator pins OSC1, OSC2 0
8 pF
C_CRYSTAL
V_IL
V_IH
Crystal load capacitance
Input ”low” voltage
Input ”high” voltage
0 12 pF
0 1.5 V
1
3.5 V_U5R V
1
1 _{for external clock applied to OSC1}
The oscillator supports direct connection of 5.33 MHz or 16.000 MHz crystals with a dedicated load capacity
of 12pF and parasitic pin capacities of up to 8pF. The IC automatically detects the oscillation frequency of the
connected crystal and controls the internal clock generator circuit accordingly. The oscillator unit also contains
a clock watch dog circuit that can generate an unconditioned IC reset if there was no clock oscillation for more
than about 20µs. This is to prevent the IC from unpredicted behavior if no clock signal is available anymore.
4.13. IC Reset
Any IC reset turns the Data Output and Parameter Output Registers to 0xF and forces the corresponding
output drivers to high impedance state. Except at Power On Reset, Data Strobe and Parameter Strobe signals
are simultaneously generated to visualize possibly changed output data to external circuitry.
The Data_Exchange_Disable flag becomes set during IC reset, prohibiting any data port activity right after IC
initialization and as long as the external circuitry was not pre-conditioned by decent parameter output data.
Consequently the AS-i master has to send a Write_Parameter call in advance of the first Data_Exchange
request to an initialized slave. Following IC initialization times apply:
Table 29: IC Initialization times
Symbol Parameter
Min Max Unit
t_INIT
Initialization time after Software Reset (generated by master
calls Reset_Slave or Broadcast_Reset) or external reset via
2 ms
DSTBn
t_INIT2
Initialization time after power on
30 ms
t_INIT3 Initialization time after power on with high capacitive load
1000 ms
1 _{guaranteed by design}
2 _{‘power on’ starts latest at VUIN = 18V, external capacitor at pin UOUT less than or equal 10µF}
3 _{CUOUT = 470µF, tINIT3 is guaranteed by design only}
Note
1
2
3
4.13.1. Power On Reset
In order to force the IC into a defined state after power up and to avoid uncontrolled switching of the digital
logic if the 5V supply (U5R) breaks down below a certain minimum level, a Power On Reset is executed under
the following conditions:
Table 30: Power On Reset Threshold Voltages
Symbol Parameter
Min Max Unit
V_POR1F V_U5R voltage to trigger internal reset procedure, falling voltage 1.2 1.7 V
V_POR1R V_U5R voltage to trigger INIT procedure, rising voltage
3.5 4.3 V
t_Low
Power-on reset pulse width
4
6
µs
1 _{guaranteed by design}
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
Note
1
1
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