SAP5SD-A-G1-T Datasheet, PDF (32/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
4.7. Parameter Port and PSTBn
The parameter port is always configured for continuous bi-directional operation. However, once IO_Code=0x7
(see Table 25), the parameter ports will return to high impedance state right after a WPAR request because
they act as data input ports or safety data ports for a following DEXG master call.
Every pin contains an NMOS open drain output driver plus a high voltage high impedance digital input stage.
Received parameter output data is stored at the Parameter Output Register and subsequently forwarded to
the open drain output drivers. A certain time (t_PI-latch) after new output data has arrived at the port, the
corresponding inputs are sampled. Due to the open drain character of the output driver, the input value results
from a wired AND combination of the parameter output value and such signals driven to the port by external
sources.
The availability of new parameter output data is signaled by the Parameter Strobe (PSTBn) signal as shown in
Figure 6.
Besides the basic I/O function, the first parameter output event after an IC reset has an additional meaning. It
enables the data exchange functionality.
Any IC reset turns the Parameter Output Register to 0xF and forces the parameter output drivers to high
impedance state. Simultaneously, a Parameter Strobe is generated, having the same t_setup timing and t_PSTBn
pulse width, as new output data would be driven.
Table 20: Timing Parameter Port
Symbol Parameter
Min Max Unit Note
t_STB
t_PSTBn
Output data is valid after PSTBn HIGH-LOW edge
Pulse width of Parameter Strobe (PSTBn)
0.0 1.5 µs
6.0 6.8 µs
1
t_PI-latch Acceptance of input data
10.5 12.5 µs
2
t_P-off
Parameter Port is at high impedance state after PSTBn HIGH- 56.0 64.5 µs
3
LOW edge
1 _{The timing of the resulting voltage signal also depends on the external pull up resistor.}
2 _{The parameter input data must be stable within the period defined by min. and max. values of tPI-latch.}
3 _{concerns the IO configuration “7” only}
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
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