SAP5SD-A-G1-T Datasheet, PDF (24/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
Table 9: SAP5 E²PROM - User and Firmware Area Content
Internal
E²PROM
Address
0
1
Bit
Position
4…0
2…0
3
4
2
3…0
4
3
4…0
4
4
3…0
5
4
3…0
6
4
0…3
7
4
3
2
1
0
8
4
3
2
1
0
9
4…0
10
11
E²PROM Cell Content Description
A4 … A0
ID1_Bit2 … ID1_Bit0
ID1_Bit3
ID1_Bit3 … ID1_Bit0
Synchronous_Data_IO
ID_Bit3 … ID_Bit0
Slave address
ID_Code_Extension_1 (user configurable)
ID_Code_Extension_1, A/B slave selection in extended
address mode
Not implemented
ID_Code_Extension_1 (manufacturer configurable)
Not implemented
Not implemented
Synchronized Data I/O mode
ID_Code
Inhibit_Write_ID1
ID2_Bit3 … ID2_Bit0
P1_Delay_Activation
IO_Bit3 … IO_Bit0
ID_Code_Extension_1 is manufacturer configurable,
refer to page 47
ID_Code_Extension_2
If flag is set, the logic value at the parameter pin P1
determines whether the Delay_Mode function is active
or inactive, refer to Table 22
IO_Code
Lock_EE_PRG
Programming of the E²PROM Firmware region is
possible as long as this flag is not set (logic LOW).
Delay_Mode
activates the Delay_Mode function, refer to Table 22
Invert_Data_In
All Data Port inputs are inverted.
Inhibit_BR01
If flag is set, the master call BR01 is not executed.
Inhibit_Watchdog
If flag is set, the watchdog is not activated.
P2_Sync_Activation
The Synchronized Data I/O mode may be activated by
Parameter bit P2 as described in Table 23 on page 36.
Ext_Addr_4I/4O_Mode 4 Input/ 4 Output Mode in Extended Address Mode
Parallel_Out_4I/4O
enables the parallel data output option in Extended
Address 4I/4O Mode
Master_Mode
Master/Repeater Mode Flag
P0_Watchdog_Activation The watchdog can be enabled/disabled by the logic
value at the parameter pin P0.
Analogue circuitry trim information
User Area
Firmware Area
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
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