SAP5SD-A-G1-T Datasheet, PDF (22/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
3 E²PROM
3.1. Overview
The SAP5 provides an on-chip E²PROM with typical write and read times according to Table 8.
Table 8: E²PROM Read and Write Times
Symbol Parameter
Min Max. Unit Note
t_{read_init}
Initialization readout time
50.0 s
1
t_{wrt_adra1}
Write time after ADRA master request
38.0 ms ²
t_{wrt_adra2}
Write time after ADRA master request
12.5 ms ³
t_{wrt_wid1u}
t_{wrt_wid1m}
Write time after WID1 master request
(user access)
Write time after WID1 master request
38.0 ms ²
25.0 ms ³
(manufacturer access)
t_{wrt_prgm}
Single cell write time
12.5 ms ⁴
1 _{Time includes readout of the configuration block. Running in Safety Mode, the User/Firmware Area and the}
Safety Area will be read out in parallel.
2 _{the Lock_EE_PRG flag is set}
3 _{the Lock_EE_PRG flag is not yet set}
4 _{concerns the programming of data in both Firmware Area and Safety Area}
For security reasons the memory area is structured in three independent data blocks and a single
configuration block containing the Security_Flag. The data blocks are named User Area, Firmware Area and
Safety Area.
The Firmware Area contains all manufacturing related configuration data (i.e. selection of optional features,
ID codes, …). It can be protected against undesired data modification by setting the Lock_EE_PRG flag to ‘1’.
The User Area contains only such data that is relevant for changes at the final application (i.e. field installation
of slave module). Because the environment where modifications of the user data may become necessary can
sometimes be rough and unpredictable, additional security was added to the programming of the User Area,
ensuring a write access cannot result in an undetected corruption of E²PROM data.
The Safety Area contains the cryptographic code table for the Safety Mode.
The E²PROM cells in User Area, Firmware Area and Safety Area have a word width of 6 bit. The sixth bit is
not shown in Table 9 and Table 11. The sixth bit of each cell represents the odd parity of the respective data
word, providing an additional data security mechanism. The programming of the parity bit is performed
automatically during the E²PROM write process and cannot be influenced by the user. Each E²PROM read
process – particularly during initialization of the SAP5 – involves an evaluation of the parity bits. In case a
wrong parity bit was found in the User Area, the entire User Area data is treated as corrupted. The IC returns
to Slave Address “0” and the ID_Code as well as the IO_Code are set to 0xF. In case a false parity bit was
found in one or more cells of the Firmware Area or the Safety Area, the status register bit S1 will be set (=’1’),
signaling the same state as the input PFAULT would be set (refer to chapter 4.16 page 46).
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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