SAP5SD-A-G1-T Datasheet, PDF (17/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
There is a defined phase relation between a parameter output event, the parameter input sampling and the
activation of the PSTBn signal. Thus it can be used to trigger external logic or a micro controller to process the
received parameter data or to provide new input data for the AS-i slave response.
See chapter 4.7 for further details.
2.3.3. Data Port Pins
The SAP5 provides a 4-bit wide data port. The outputs work independently from each other allowing a
maximum of 4 output devices to be connected to the SAP5. The directions of the Data Port pins are set
through the IO_Code, see chapter 4.9.
The data port is accompanied by the data strobe signal DSTBn. There is a defined phase relation between a
data output event, the input data sampling and the activation of the DSTBn signal. Thus, it can be used to
trigger external logic or a micro controller to process the received data or to provide new input data for the AS-
i slave response. See chapter 4.8 for further details.
2.3.4. Data Input Inversion
By default the logic signal (HIGH / LOW) that is present at the data input pins during the input sampling phase
is transferred without modification to the send register, which is interfaced by the UART. By that, the signal
becomes directly part of the slave response.
Some applications work with inverted logic levels. To avoid additional external inverters, the input signal can
be inverted by the SAP5 before transferring it to the send register. The inversion of the input signals can be
done jointly for all data input pins. See chapter 4.8.
2.3.5. Data Input Filtering
To prevent input signal bouncing from being transferred to the AS-i Master, the data input signals can be
digitally filtered. Activation of the filter is done jointly either by E²PROM configuration or by the logic state of
parameter port pin P2. For more detailed information refer to chapter 4.8.
2.3.6. Synchronous Data I/O Mode
AS-i Complete Specification V3.0 newly defines a synchronous data I/O feature, that allows a number of
slaves in the network to switch their outputs at the same time and to have their inputs sampled
simultaneously. This feature is especially useful if more than 4-bit wide data is to be provided synchronously
to an application.
The synchronization point was defined to the data exchange event of the slave with the lowest address in the
network. This definition relies on the cyclical slave polling with increasing slave addresses per cycle that is
one of the basic communication principles of AS-i. The IC always monitors the data communication and
detects the change from a higher to a lower slave address. If such a change was recognized, the IC assumes
that the slave with the lower address has the lowest address in the network.
There are some special procedures that become active during the start of synchronous I/O mode operation
and if more than three consecutive telegrams were sent to the same slave address. This is described in more
detail in chapter 4.8.3.
2.3.7. 4 Input / 4 Output processing in Extended Address Mode
A new feature of AS-i Complete Specification v3.0 is also support of 4-bit wide output data in Extended
Address Mode. In Extended Address Mode it was, up to Complete Specification v2.11, only possible to send
three data output bits from the master to the slave because telegram bit I3 is used to select between A- and B-
slave type for extended slave addressing (up to 62 slaves per network). In normal address mode I3 carries
output data for pin D3.
The new definition introduces a multiplexed data transfer, so that all 4-bits of the data output port can be used
again. A first AS-i cycle transfers the data for a 2-bit output nibble only, while the second AS-i cycle transfers
the data for the contrary 2-bit nibble. Nibble selection is done by the remaining third bit. To ensure continuous
alternation of bit information I2 and thus continued data transfer to both nibbles, a special watchdog was
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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