SAP5SD-A-G1-T Datasheet, PDF (38/63 Pages) List of Unclassifed Manufacturers – Universal Actuator-Sensor Interface IC

SAP5S / SAP51
Universal Actuator-Sensor Interface IC
Following coding applies:
Table 24: Meaning of master call bits I0 … I3 in Ext_Addr_4I/4O_Mode
Master Call Operation / Meaning
Bit
Parallel_Out_4I/4O = ‘0’
Parallel_Out_4I/4O = ‘1’
I2 = ‘0’
I0
D2 = I0
I1
D3 = I1
D1 = unchanged
D0 = unchanged
I2 = ‘1’
D2 = unchanged
D3 = unchanged
D1 = I1
D0 = I0
I2 = ‘0’
D2 = I0
D3 = I1
D1 = DO1_tmp ²
D0 = DO0_tmp ²
I2 = ‘1’
D2 = unchanged ¹
D3 = unchanged ¹
D1 = unchanged ¹
D0 = unchanged ¹
DO1_tmp = I1
DO0_tmp = I0
I2
I2: /Sel-bit for transmission to Bank_1 (D0/D1) / Bank_2 (D2/D3)
I3
I3: /Sel-bit for A-Slave/B-Slave addressing
NOTES:
1 _{If I2 = ‘1’ then I0/I1 are directed to temporary data output registers DO0_tmp/DO1_tmp}
2 _{If I2 = ‘0’ then I0/I1 are directed to the data output registers D2/D3 and DO0_tmp/DO1_tmp are directed to}
the data output registers D0/D1
In order to ensure that both Bank_1 and Bank_2 data are refreshed continuously, the SAP5 supervises the
alternation of the I2 Sel-bit by use of the 4I/4O Watchdog. The 4I/4O Watchdog gets activated as soon as
 The Communication Watchdog is activated (refer to Table 33).
 The IC is operated in Extended Address Mode and the Ext_Addr_4I/4O_Mode flag is set (=’1’) in the
E²PROM.
 Slave address is unequal to zero (0).
 No E²PROM write access is active.
 The slave is activated, i.e. the Data_Exchange_Disable flag is cleared.
If there is no alternation of the I2 bit for more than 327ms (+16ms) ms after the activation of the slave the
4I/4O Watchdog takes the following actions:
 It generates Data and Parameter Strobe signals at the DSTBn an PSTBn pins with timing according to
Figure 6 and Figure 7.
 After DSTBn an PSTBn strobe generation finished, the 4I/4O Watchdog invokes an unconditioned IC
Reset. It sets the Data_Exchange_Disable flag and - afterwards - starts the IC initialization procedure,
switching all Data and Parameter Outputs inactive.
Input data is captured and returned to the master at every cycle, independent of the value of information bit I2
4.8.5. Special function of DSTBn
Beside its standard output function the Data Strobe Pin serves as external reset input for all operational
modes of the IC. Pulling the DSTBn pin LOW for more than a minimum reset time generates an unconditioned
reset of the IC, which is immediately followed by an initialization of the state machine (E²PROM read out).
Further information on the IC reset behavior, especially in regard to the signal timing, can be found at chapter
4.13 IC Reset.
Data Sheet
July 17, 2012
© 2012 Zentrum Mikroelektronik Dresden AG — Rev. 3.1
All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without
the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to
changes without notice.
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