SED1330F Datasheet, PDF (84/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

5.0 Display Control Functions
5.2.3 Display Scan Timing
Figure 44 shows the basic timing of the SED1330F/
1335F/1336F. One display memory read cycle takes
nine periods of the system clock, φ0 (f_OSC). This cycle
repeats (C/R + 1) times per display line.
When reading, the display memory pauses at the end
of each line for (TC/R – C/R) display memory read
5.2.3
cycles, though the LCD drive signals are still gener-
ated. TC/R may be set to any value within the con-
straints imposed by C/R, f_OSC, f_FR, and the size of the
LCD panel, and it may be used to fine tune the frame
frequency. The microprocessor may also use this
pause to access the display memory data.
φ0
VCE
VA
T0
Character read interval
T1
Display read cycle interval
Graphics read interval
T2
Graphics generator
read interval
Figure 52. Display memory basic read cycle
Display period
TC/R
C/R
Divider frequency
period
Line 1
O
R
2
O
R
Frame
3
O
R
period
•
•
•
•
•
(L/F)
O
R
LP
Note: The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.
Figure 53. Relationship between TC/R and C/R
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