SED1330F Datasheet, PDF (115/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

8.2 – 8.2.2
8.2 Display Memory Interface
8.2.1 Static RAM
The figure below shows the interface between an 8K
× 8 static RAM and the SED1330F/1335F/1336F.
8.0 Description of Circuit Blocks
Note that bus buffers are required if the bus is heavily
loaded.
VA0 to VA12
VA13 to VA15
VCE
SED1335F/
1336F
HC138
A
to Y
C
V_DD
A0 to A12
CE1
CE2
6264 SRAM
OE
VR/W
I/O1 to I/O8
R/W
I/O1 to I/O8
Figure 74. Static RAM interface
8.2.2 Supply Current during Display Memory Access
The 24 address and data lines of the SED1330F/
1335F/1336F cycle at one-third of the oscillator fre-
quency, f_OSC. The charge and discharge current on
these pins, I_VOP, is given by the equation below.
When I_VOP exceeds I_OPR, it can be estimated by:
I_VOP ∝ C V f
where C is the capacitance of the display memory
bus, V is the operating voltage, and f is the operating
frequency.
If V_OPR = 5.0V, f = 1.0 MHz, and the display memory
bus capacitance is 1.0 pF per line:
I_VOP ≤ 120 µA / MHz × pF
To reduce current flow during display memory ac-
cesses, it is important to use low-power memory, and
to minimize both the number of devices and the
parasitic capacitance.
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