SED1330F Datasheet, PDF (75/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.5.7.2 – 4.5.7.3
4.0 Specifications
4.5.7.2 SED1335F
Signal
XSCL
XD0 to
XD3
LP
WF
YD
Symbol
tr
tf
tCX
tWX
tDH
tDS
tLS
tWL
tLD
tDF
tDHY
Parameter
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min max min max
Rise time
—
30
—
40
Fall time
—
30
—
40
Shift clock cycle time
4tC
—
4tC
—
XSCL clock pulsewidth 2tC – 60 — 2tC – 60 —
X data hold time
2tC – 50 — 2tC – 50 —
X data setup time
2tC – 100 — 2tC – 105 —
Latch data setup time 2tC – 50 — 2tC – 50 —
LP pulsewidth
4tC – 80 — 4tC – 120 —
LP delay time from XSCL 0
—
0
—
Permitted WF delay
—
50
—
50
Y data hold time
2tC – 20 — 2tC – 20 —
Ta = –20 to 75°C
Unit Condition
ns
ns
ns
ns
ns
CL =
ns
100 pF
ns
ns
ns
ns
ns
4.5.7.3 SED1336F
Ta = –20 to 75°C
Signal Symbol
Parameter
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Unit Condition
min max min max
tr Rise time
—
30
—
35
ns
tf Fall time
—
30
—
35
ns
tCX Shift clock cycle time
4tC
—
4tC
—
ns
XSCL
tWX XSCL clock pulsewidth 2tC – 60 — 2tC – 60 —
ns
XD0 to ^{tDH X data hold time}
XD3
tDS X data setup time
2tC – 50 — 2tC – 50 —
2tC – 100 — 2tC – 100 —
tLS Latch data setup time 2tC – 50 — 2tC – 50 —
ns
CL =
ns
100 pF
ns
LP
tWL LP pulsewidth
4tC – 80 — 4tC – 100 —
ns
tLD LP delay time from XSCL 0
—
0
—
ns
WF
tDF Permitted WF delay
—
50
—
50
ns
YD
tDHY Y data hold time
2tC – 20 — 2tC – 20 —
ns
Note: The SED1335F/1336F reads display memory data from the address of the top left corner of the display screen, then scans
horizontally until it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data
is sent starting from the left side of the display line.
268-0.4 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}