SED1330F Datasheet, PDF (112/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

8.0 Description of Circuit Blocks
synchronizes its processing to the SED1330F/1335F/
1336F’s timing. When writing, the microprocessor
first issues the MWRITE command. It then repeatedly
writes display data to the SED1336F using the sys-
tem bus timing. This ensures that the microprocessor
is not slowed down even if the display memory
access times are slower than the system bus access
times. See Figure 70.
8.1.2.3
When reading, the microprocessor first issues the
MREAD command, which causes the SED1330F/
1335F/1336F to load the first read data into its output
buffer. The microprocessor then reads data from the
SED1330F/1335F/1336F using the system bus tim-
ing. With each read, the SED1330F/1335F/1336F
reads the next data item from the display memory
ready for the next read access. See Figure 71.
Microprocessor
WR
D0 to D7
Display memory
WR/W
VD0 to VD7
tCYC
Command write
Data write
Data write
Figure 70. Display memory write cycle
WR
Microprocessor
RD
D0 to D7
Display memory
WR/W
VD0 to VD7
Command write
tCYC
Data read
Figure 71. Display memory read cycle
Data read
Note: A possible problem with the display memory read cycle is that the system bus access time, t_ACC, does not depend on the display
memory access time, t_ACV. The microprocessor may only make repeated reads if the read loop time exceeds the SED1330F/
1335F/1336F cycle time, t_CYC. If it does not, NOP instructions may be inserted in the program loop. t_ACC, t_ACV and t_CYC limits
are given in Section 4.3.
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