SED1330F Datasheet, PDF (59/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.4.5.1
4.4 SED1330 Timing Diagrams
4.4.5.1 SED1330F
Signal Symbol
Parameter
EXT Ø0
XSCL
XD0
to XD3
LP
XECL
WF
YSCL
YD
tC
tr
tf
tCX
tWX
tDH
tDS
tLS
tWL
tL1
tL2
tS1
tS1
tWXE
tDF
tLD
tWY
tDHY
Clock cycle
VCE high level pulse width
VCE low level pulse width
Shift clock cycle time
XSCL clock pulse width
X-data hold time
X-data setup time
Latch data setup time
LP signal pulse width
XECL setup time
XECL data hold time
Enable setup time
Enable delay time
XECL clock pulse width
Time allowance of WF delay
LP delay time against YSCL
YSCL clock pulse width
Y-data hold time
Rating
min
max
100
—
—
35
—
35
4tc
—
tCX2–80
—
tCX2–100
—
tCX2–100
—
tCX2–100
—
tCX4–80
—
tCX3–100
—
tC–30
—
tC–30
—
tC–30
—
tCX3–80
—
—
100
tCX4–100
—
tCX4–80
—
tCX6–100
—
4.0 Specifications
Ta = –20 to 75°C
Unit
Condition
ns
ns
ns
ns
ns
ns
VDD = 5.0V
ns
±10%
ns
CL=150F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
268-0.4 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}