SED1330F Datasheet, PDF (70/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.0 Specifications
4.5.4.2
4.5.4.2 SED1336F
Ta = –20 to 75°C
Signal Symbol
Parameter
VDD = 4.5 to 5.5V VDD = 3.0 to 4.5V
Unit Condition
min max min max
EXT φ0 tC Clock period
100
—
125
—
ns
tW
VCE HIGH-level pulse-
width
tC – 50
—
tC – 50
—
ns
VCE
tCE
VCE LOW-level pulse-
width
2tC – 30
—
2tC – 30
—
ns
tCYW Write cycle time
3tC
—
3tC
—
ns
tAHC
Address hold time from
falling edge of VCE
2tC – 30
—
2tC – 40
—
ns
VA0 to
VA15
tASC
tCA
tAS
Address setup time to
falling edge of VCE
Address hold time from
rising edge of VCE
Address setup time to
falling edge of VWR
tC – 70
0
0
— tC – 100 —
—
0
—
—
0
—
ns
ns _{CL = 100}
pF
ns
tAH2
Address hold time from
rising edge of VWR
10
—
10
—
ns
tWSC
Write setup time to falling
edge of VCE
tC – 80
— tC – 110 —
ns
VWR
tWHC
Write hold time from fall-
ing edge of VCE
2tC – 20
—
2tC – 20
—
ns
tDSC
Data input setup time to
falling edge of VCE
tC – 85
— tC – 120 —
ns
VD0 to
VD7
tDHC
Data input hold time
from falling edge of VCE
2tC – 30
—
2tC – 30
—
ns
tDH2
Data hold time from
rising edge of VWR
5
50
5
50
ns
Note: VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
70 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}