SED1330F Datasheet, PDF (56/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.0 Specifications
4.4 SED1330 Timing Diagrams
4.4.3 Display memory READ timing
EXT^φO
VCE
VA0~VA15
VR/W
VD0~VD7
t_C
t_W
t_CE
t_CYR
t_ASC
t_RCS
t_CEA
t_ACY
t_AHC
4.4.3 – 4.4.3.1
t_W
t_RCH
t_CE3
t_OH2
Figure 34. Display memory READ timing
4.4.3.1 SED1330F
Signal Symbol
Parameter
EXT Ø0
VCE
VA0
to VA15
VR/W
VD0
to VD7
tC
tW
tCE
tCYR
tASC
tAHC
tRCS
tRCH
tACV
tCEA
tOH2
tCE2
Clock cycle
VCE high level pulse width
VCE low level pulse width
Read cycle time
VCE address setup time (fall)
VCE address hold time (fall)
VCE read cycle setup time (fall)
VCE read cycle hold time (fall)
Address access time
VCE access time
Output data hold time
VCE data off time
Rating
min
max
100
—
tc–40
—
2tc–40
—
(1)
—
tc–45
—
2tc–40
—
tc–45
—
tc/2–35
—
—
(2)
—
(3)
0
—
0
—
Note: 1.
2.
3.
t_CYR
t_ACV
t_CEA
= 3t_C
= 3t_C –120
= 2t_C –120
Ta = –20 to 75°C
Unit
Condition
ns
ns
ns
ns
ns
CL = 100pF
ns
+1TTL
ns
ns
ns
ns
ns
ns
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