SED1330F Datasheet, PDF (23/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

2.4.4 – 2.4.5
2.0 Pin Description
2.4.4 Display Memory Control
The SED1330F/1335F/1336F can directly access static
RAM and PROM. The designer may use a mixture of
these two types of memory to achieve an optimum
trade-off between low cost and low power consumption.
Pin Name
VA0 to VA15
VD0 to VD7
VR/W
VRD
VCE
VWR
Function
16-bit display memory address. When accessing character generator RAM or ROM, VA0 to
VA3, reflect the lower 4 bits of the row counter.
8-bit tristate display memory data bus. These pins are enabled when VR/W is LOW.
Active-LOW display memory write control output (SED1330).
Active-LOW display memory read control output (SED1335/6).
Active-LOW static memory standby control signal. VCE can be used with CS.
Active-LOW display memory write control output (SED1335/6).
2.4.5 LCD Drive Signals
In order to provide effective low-power drive for LCD
matrixes, the SED1330F/1335F/1336F can directly
control both the X- and Y-drivers using an enable
chain.
Pin Name
Function
XD0 to XD3
4-bit X-driver (column drive) data outputs. Connect these outputs to the inputs of the X-driver
chips.
XSCL
The falling edge of XSCL latches the data on XD0 to XD3 into the input shift registers of the
X-drivers. To conserve power, this clock halts between LP and the start of the following display
line (see Section 4.3.7).
XECL
The falling edge of XECL (SED1330F/1335F only) triggers the enable chain cascade for the
X-drivers (SED1600/SED1180). Every 16th clock pulse is output to the next X-driver.
LP latches the signal in the X-driver shift registers into the output data latches. LP is a falling-
LP
edge triggered signal, and pulses once every display line.
Connect LP to the Y-driver shift clock on modules that use the SED1600 and SED1610 drivers.
WF
LCD panel AC drive output. The WF period is selected to be one of two values with SYSTEM
SET command.
YSCL
The falling edge of YSCL (SED1330F/1335F only) latches the data on YD into the input shift
registers of the Y-drivers. YSCL is not used with the SED1600, SED1610 or other driver ICs
which use LP as the Y-driver shift clock.
YD is the data pulse output for the Y drivers. It is active during the last line of each frame, and
YD
is shifted through the Y drivers one by one (by YSCL), to scan the display’s common
connections.
Power-down output signal. YDIS is HIGH while the display drive outputs are active.
YDIS
YDIS goes LOW one or two frames after the sleep command is written to the SED1330F/
1335F/1336F. All Y-driver outputs are forced to an intermediate level (de-selecting the display
segments) to blank the display. In order to implement power-down operation in the LCD unit,
the LCD power drive supplies must also be disabled when the display is disabled by YDIS.
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