SED1330F Datasheet, PDF (57/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.4.4 – 4.4.4.1
4.4 SED1330 Timing Diagrams
4.4.4 Display memory WRITE timing
4.0 Specifications
EXTφO
VCE
VA0~VA15
VWR
VD0~VD7
tC
tW
tASC
tAS tWSC
tOSC
tCE
tAHC
tCYW
tWHC
tOHC
tCA
tAH2
tOH2
Figure 35. Display memory WRITE timing
4.4.4.1 SED1330F
Signal Symbol
Parameter
EXT Ø0
VCE
VA0
to VA15
VR/W
VD0
to VD7
tC
tW
tCE
tCYW
tAHC
tASC
tCA
tAS
tAH2
tWSC
tWHC
tDSC
tDHC
tDH2
Clock cycle
VCE high level pulse width
VCE low level pulse width
Write cycle time
VCE address hold time (fall)
VCE address setup time (fall)
VCE address hold time (rise)
VR/W address setup time (fall)
VR/W address hold time (rise)
VCE write setup time (fall)
VCE write hold time (fall)
VCE data input setup time (fall)
VCE data input hold time (fall)
VR/W data hold time (rise)
Rating
min
max
100
—
tc–40
—
2tc–40
—
3tc
—
2tc–40
—
tc–55
—
5
—
0
—
15
—
tc–55
—
tc2–40
—
twsc–10
—
2tc–30
—
10*
50
* Lines VD0 to VD7 are latched.
Ta = –20 to 75°C
Unit
Condition
ns
ns
ns
ns
ns
ns
CL = 100pF
ns
+1TTL
ns
ns
ns
ns
ns
ns
ns
268-0.4 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}