SED1330F Datasheet, PDF (66/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.0 Specifications
4.5.3 Display Memory Read Timing
4.5.3 – 4.5.3.1
EXTΦ0
VCE
VA0 to VA15
VRD
VD0 to VD7
(SED1335F)
tC
tW
tCE
tASC
tCYR
tAHC
tRCS
tACV
tCEA
tW
tRCH
tCE3
tOH2
Figure 41. Display memory read timing
4.5.3.1 SED1335F
Signal
EXT φ0
VCE
VA0 to
VA15
VRD
VD0 to
VD7
Symbol
tC
tW
tCE
tCYR
tASC
tAHC
tRCS
tRCH
tACV
tCEA
tOH2
tCE3
Parameter
Clock period
VCE HIGH-level pulse-
width
VCE LOW-level pulse-
width
Read cycle time
Address setup time to
falling edge of VCE
Address hold time from
falling edge of VCE
Read cycle setup time to
falling edge of VCE
Read cycle hold time
from rising edge of VCE
Address access time
VCE access time
Output data hold time
VCE to data off time
VDD = 4.5 to 5.5V VDD = 2.7 to 4.5V
min max min max
100
—
125
—
tC – 50 — tC – 50 —
2tC – 30 — 2tC – 30 —
3tC
—
3tC
—
tC – 70 — tC – 100 —
2tC – 30 — 2tC – 40 —
tC – 45 — tC – 60 —
0.5tC
—
0.5tC
—
— 3tC – 100 — 3tC – 115
— 2tC – 80 — 2tC – 90
0
—
0
—
0
—
0
—
Ta = –20 to 75°C
Unit Condition
ns
ns
ns
ns
ns
CL = 100
ns
pF
ns
ns
ns
ns
ns
ns
66 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}