SED1330F Datasheet, PDF (74/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

4.0 Specifications
4.5.7.1 SED1330F
Signal Symbol
Parameter
XSCL
XD0
to XD3
LP
XECL
WF
YSCL
YD
tr
tf
tCX
tWX
tDH
tDS
tLS
tWL
tL1
tL2
tS1
tS1
tWXE
tDF
tLD
tWY
tDHY
VCE high level pulse width
VCE low level pulse width
Shift clock cycle time
XSCL clock pulse width
X-data hold time
X-data setup time
Latch data setup time
LP signal pulse width
XECL setup time
XECL data hold time
Enable setup time
Enable delay time
XECL clock pulse width
Time allowance of WF delay
LP delay time against YSCL
YSCL clock pulse width
Y-data hold time
Rating
min
max
—
35
—
35
4tc–70
—
2tC–80
—
2tC–100
—
2tC–100
—
2tC–100
—
4tC–80
—
3tC–100
—
tC–30
—
tC–30
—
tC–30
—
3tC–80
—
—
100
4tC–100
—
4tC–80
—
6tC–100
—
4.5.7
Ta = –20 to 75°C
Unit
Condition
ns
ns
ns
ns
ns
VDD = 5.0V
ns
±10%
ns
CL=150F
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The E-1330 reads display memory data from the address of the top left corner of the display screen, then scans horizontally until
it reaches the address for the bottom right corner of the display screen. Therefore, each line of X-driver data is sent starting from
the left side of the display line.
2. The E-1330 uses nine cycles of ø0 as the basic cycle (t_c). The XSCL waveform is shown in the following figure.
ø0
XSCL
4 tC
5 t_C
74 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}