SED1330F Datasheet, PDF (111/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

8.0 – 8.1.2.3
8.0 Description of Circuit Blocks
8.1 Microprocessor Interface
8.1.1 System Bus Interface
SEL1, SEL2 (SED1330F and SED1335F only), A0,
RD, WR and CS are used as control signals for the
microprocessor data bus. A0 is normally connected to
the lowest bit of the system address bus. SEL1 and
SEL2 change the operation of the RD and WR pins to
enable interfacing to either an 8080 or 6800 family
bus, and should have either a pull-up or a pull-down
resistor.
With microprocessors using an 8080 family interface,
the SED1330F/1335F/1336F is normally mapped into
the I/O address space.
8.1.1.1 8080 series
Table 29. 8080 series interface signals
A0 RD WR
Function
0 0 1 Status flag read
1
0
1
Display data and cursor address
read
0 1 0 Display data and parameter write
1 1 0 Command write
8.1.1.2 6800 series
Table 30. 6800 series interface signals
A0 RD WR
Function
0 1 1 Status flag read
1
1
1
Display data and cursor address
read
0 0 1 Display data and parameter write
1 0 1 Command write
8.0 Description of Circuit Blocks
8.1.2 Microprocessor Synchronization
The SED1330F/1335F/1336F interface operates at
full bus speed, completing the execution of each
command within the cycle time, t_CYC. The controlling
micro-processor’s performance is thus not hampered
by polling or handshaking when accessing the
SED1330F/1335F/1336F.
Display flicker may occur if there is more than one
consecutive access that cannot be ignored within a
frame. The microprocessor can minimize this either
by performing these accesses intermittently, or by
continuously checking the status flag (D6) and waiting
for it to become HIGH.
8.1.2.1 Display Status Indication Output
(For SED1336 only)
When CS, A0 and RD are LOW, D6 functions as the
display status indication output. It is HIGH during the
TV-mode vertical retrace period or the LCD-mode
horizontal retrace period, and LOW, during the period
the controller is writing to the display. By monitoring
D6 and writing to the data memory only during retrace
periods, the display can be updated without causing
screen flicker.
8.1.2.2 Internal Register Access
The SYSTEM SET and SLEEP IN commands can be
used to perform input/output to the SED1330F/1335F/
1336F independently of the system clock frequency.
These are the only commands that can be used while
the SED1330F/1335F/1336F is in sleep mode.
8.1.2.3 Display Memory Access
The SED1330F/1335F/1336F supports a form of
pipelined processing, in which the microprocessor
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