SED1330F Datasheet, PDF (117/148 Pages) List of Unclassifed Manufacturers – LCD Controller ICs

8.4 – 8.5
Read Status Flag
No
D6 = 1?
Yes
Data Input
No
Data Input ?
Yes
Figure 78. Flowchart for busy flag checking
8.0 Description of Circuit Blocks
8.5 Reset
The SED1330F requires a reset pulse at least 1 ms
long after power-on in order to re-initialize its internal
state. The SED1335F/1336F requires a minimum
reset pulse of 200µs.
During reset, the LCD drive signals XD, LP and FR are
halted.
For maximum reliability, it is not recommended to
apply a DC voltage to the LCD panel while the
SED1330F/1335F/1336F is reset. Turn off the LCD
power supplies for at least one frame period after the
start of the reset pulse.
The SED1330F/1335F/1336F cannot receive com-
mands while it is reset. Commands to initialize the
internal registers should be issued soon after a reset.
A delay of 3 ms (maximum) is required following the
rising edges of both RES and V_DD to allow for system
stabilization.
VDD
RES
0.7 VDD
200µs reset pulse
0.3 VDD
Figure 79. Reset timing
268-0.4 _{S-MOS Systems, Inc. • 2460 North First Street • San Jose, CA 95131 • Tel: [phone] • Fax: [phone]}