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M13S32321A_08 Datasheet, PDF (8/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM
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ESMT
M13S32321A
AC Timing Parameter & Specifications-continued
Parameter
Symbol
-5
min
max
-6
min
max
Half Clock Period
tHP
tCLmin or tCHmin
-
tCLmin or tCHmin
-
ns
DQ-DQS output hold
time
tQH
tHP-0.5
-
tHP-0.5
-
ns
ACTIVE to PRECHARGE
command
tRAS
40
120K
45
120Kns
ns
Row Cycle Time
tRC
60
-
66
-
ns
AUTO REFRESH Row Cycle
Time
tRFC
70
-
72
-
ns
ACTIVE to READ,WRITE
delay
tRCD
4
-
4
-
tCK
PRECHARGE command
period
tRP
4
-
4
-
tCK
ACTIVE to READ with
AUTOPRECHARGE
tRAP
18
120K
18
120K
ns
command
ACTIVE bank A to ACTIVE
bank B command
tRRD
2
-
2
-
tCK
Write recovery time
tWR
2
-
2
-
tCK
Write data in to READ
command delay
tWTR
2
-
2
-
tCK
Col. Address to Col. Address
delay
tCCD
1
-
1
-
tCK
Average periodic refresh
interval
tREFI
-
7.8
-
7.8
us
Write preamble
tWPRE
0.25
-
0.25
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Clock to DQS write preamble
setup time
tWPRES
0
-
0
-
ns
Load Mode Register /
Extended Mode register
tMRD
2
-
2
-
tCK
cycle time
Exit self refresh to READ
command
tXSRD
200
-
200
-
tCK
Exit self refresh to
non-READ command
tXSNR
75
-
75
-
ns
Autoprecharge write
recovery+Precharge time
tDAL
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
tCK
(tRP/tCK)
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
8/50
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