M13S32321A_08 Datasheet, PDF (2/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Functional Block Diagram
CLK
CLK
CKE
Clock
Generator
Address
Mode Register &
Extended Mode
Register
Row
Address
Buffer
&
Refresh
Counter
CS
RAS
CAS
WE
Column
Address
Buffer
&
Refresh
Counter
M13S32321A
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder
Data Control Circuit
DM
DQ
Pin Arrangement
CLK, CLK
DLL
DQS
DQS
DQ29
81
VSSQ
82
DQ30
83
DQ31
84
VSS
85
VDDQ
86
N.C
87
N.C
88
N.C
89
N.C
90
N.C
91
VSSQ
92
N.C
93
DQS
94
VDDQ
95
VDD
96
DQ0
97
DQ1
98
VSSQ
99
DQ2
100
50
A7
49
A6
48
A5
47
A4
46
VSS
45
A9
44
N.C
43
N.C
42
N.C
41
N.C
40
N.C
39
N.C
38
N.C
37
N.C
36
N.C
35
VDD
34
A3
33
A2
32
A1
31
A0
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
2/50