M13S32321A_08 Datasheet, PDF (19/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
Read Interrupted by a Precharge
A Burst Read operation can be interrupted by precharge of the same bank. The minimum 1 clock is required for the read to
precharge intervals. A precharge command to output disable latency is equivalent to the CAS latency.
<Burst Length = 8, CAS Latency = 3>
CLK
CLK
COMMAND
0
1
1tCK
READ
Prech arg e
2
NOP
3
NOP
4
NOP
5
NOP
6
NOP
7
NOP
8
NOP
CAS Latency=3
DQS
DQ's
Dout 0 Dout 1 Dout 2 Dout 3 Dout 4 Dout 5 Dout 6 Dout 7
Interrupted by precharge
When a burst Read command is issued to a DDR SDRAM, a Precharge command may be issued to the same bank before the
Read burst is complete. The following functionality determines when a Precharge command may be given during a Read burst and
when a new Bank Activate command may be issued to the same bank.
1. For the earliest possible Precharge command without interrupting a Read burst, the Precharge command may be given on the
rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency. A new Bank
Activate command may be issued to the same bank after t_RP (RAS precharge time).
2. When a Precharge command interrupts a Read burst operation, the Precharge command may be given on the rising clock edge
which is CL clock cycles before the last data from the interrupted Read burst where CL is the CAS Latency. Once the last
data word has been output, the output buffers are tristated. A new Bank Activate command may be issued to the same bank
after t_RP.
3. For a Read with autoprecharge command, a new Bank Activate command may be issued to the same bank after t_RP where t_RP
begins on the rising clock edge which is CL clock cycles before the end of the Read burst where CL is the CAS Latency.
During Read with autoprecharge, the initiation of the internal precharge occurs at the same time as the earliest possible
external Precharge command would initiate a precharge operation without interrupting the Read burst as described in 1 above.
4. For all cases above, t_RP is an analog delay that needs to be converted into clock cycles. The number of clock cycles between a
Precharge command and a new Bank Activate command to the same bank equals t_RP / t_CK (where t_CK is the clock cycle time)
with the result rounded up to the nearest integer number of clock cycles.
In all cases, a Precharge operation cannot be initiated unless t_RAS(min) [minimum Bank Activate to Precharge time] has been
satisfied. This includes Read with autoprecharge commands where t_RAS(min) must still be satisfied such that a Read with
autoprecharge command has the same timing as a Read command followed by the earliest possible Precharge command which
does not interrupt the burst.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
19/50