M13S32321A_08 Datasheet, PDF (15/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Row Active
M13S32321A
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the
clock (CLK). The DDR SDRAM has four independent banks, so two Bank Select addresses (BA0, BA1) are required. The Bank
Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS delay time (t_RCD min).
Once a bank has been activated, it must be precharged before another Bank Activation command can be applied to the same bank.
The minimum time interval between interleaved Bank Activation command (Bank A to Bank B and vice versa) is the Bank to Bank
delay time (t_RRD min).
Bank Activation Command Cycle ( CAS Latency = 3)
0
1
2
CLK
CLK
Address
Command
Bank A
Row Ad dr.
Bank A
Col. Addr.
RAS-CAS delay (tRCD)
Bank A
Activate
NOP
Write A
with Au to
Prech arg e
ROW Cycle Time (tRC)
Bank B
Row Ad dr.
Bank A
Row. Addr.
RAS-RAS delay (tRRD)
Bank B
Activate
NOP
Bank A
Activate
: Don't Care
Read Bank
This command is used after the row activate command to initiate the burst read of data. The read command is initiated by
activating CS , CAS , and deasserting WE at the same clock sampling (rising) edge as described in the command truth table.
The length of the burst and the CAS latency time will be determined by the values programmed during the MRS command.
Write Bank
This command is used after the row activate command to initiate the burst write of data. The write command is initiated by
activating CS , CAS , and WE at the same clock sampling (rising) edge as describe in the command truth table. The length of
the burst will be determined by the values programmed during the MRS command.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
15/50