M13S32321A_08 Datasheet, PDF (7/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
AC Timing Parameter & Specifications
(V_DD = 2.375V~2.625V, V_DDQ=2.375V~2.625V, T_A =0 °C to 70 °C )(Note)
Parameter
Clock Period
Symbol
CL3
t_CK
CL4
-5
min
max
5.0
10
-
-
-6
min
max
6.0
10
ns
-
-
Access time from CLK/ CLK
CLK high-level width
CLK low-level width
Data strobe edge to clock edge
Clock to first rising edge of DQS delay
Data-in and DM setup time (to DQS)
Data-in and DM hold time (to DQS)
DQ and DM input pulse width (for each input)
Input setup time (fast slew rate)
Input hold time (fast slew rate)
Control and Address input pulse width
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CLK rising-setup time
DQS falling edge from CLK rising-hold time
Data strobe edge to output data edge
Data-out high-impedance window from
CLK/ CLK
Data-out low-impedance window from
CLK/ CLK
t_AC
t_CH
t_CL
t_DQSCK
t_DQSS
t_DS
t_DH
t_DIPW
t_IS
t_IH
t_IPW
t_DQSH
t_DQSL
t_DSS
t_DSH
t_DQSQ
t_HZ
t_LZ
-0.7
0.45
0.45
-0.7
0.75
0.5
0.5
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
+0.7
0.55
0.55
+0.7
1.25
-
-
-
-
-
-
0.6
0.6
-
-
0.4
+0.7
+0.7
-0.7
0.45
0.45
-0.7
0.75
0.5
0.5
1.75
1.0
1.0
2.2
0.4
0.4
0.2
0.2
-
-0.7
-0.7
+0.7
ns
0.55
t_CK
0.55
t_CK
+0.7
ns
1.25
t_CK
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
0.6
t_CK
0.6
t_CK
-
t_CK
-
t_CK
0.4
ns
+0.7
ns
+0.7
ns
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
7/50