M13S32321A_08 Datasheet, PDF (30/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
Current State _CS
H
L
L
PRE-CHARGIN ^L
G
L
L
L
L
H
L
L
ROW
L
ACTIVATING _L
L
L
L
H
L
L
L
WRITE
RECOVERING
L
L
L
L
L
RAS CAS WE
XXX
HHH
HH L
HLX
L HH
LHL
L
L
H
L
L
L
XXX
HHH
HH L
HLX
L HH
LHL
L
L
H
L
L
L
XXX
HHH
HH L
HLH
H
L
L
L HH
LHL
L
L
H
L
L
L
Address
X
X
BA
BA, CA, A8
BA, RA
BA, A8
X
Op-Code Mode-Add
X
X
BA
BA, CA, A8
BA, RA
BA, A8
X
Op-Code Mode-Add
X
X
BA
BA, CA, A8
BA, CA, A8
BA, RA
BA, A8
X
Op-Code Mode-Add
Command
DESEL
NOP
Burst Stop
READ/WRITE
Active
PRE / PREA
Refresh
MRS
DESEL
NOP
Burst Stop
READ / WRITE
Active
PRE / PREA
Refresh
MRS
DESEL
NOP
Burst Stop
READ
WRITE
Active
PRE / PREA
Refresh
MRS
Action
NOP (Idle after t_RP)
NOP (Idle after t_RP)
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
NOP*4 (Idle after t_RP)
ILLEGAL
ILLEGAL
NOP (ROW Active after t_RCD)
NOP (ROW Active after t_RCD)
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
NOP
NOP
ILLEGAL*2
ILLEGAL*2
WRITE
ILLEGAL*2
ILLEGAL*2
ILLEGAL
ILLEGAL
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
30/50