M13S32321A_08 Datasheet, PDF (24/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
DM masking
The DDR SDRAM has a data mask function that can be used in conjunction with data write cycle. Not read cycle. When the
data mask is activated (DM high) during write operation, DDR SDRAM does not accept the corresponding data. (DM to data-mask
latency is zero) DM must be issued at the rising or falling edge of data strobe.
<Burst Length = 8>
0
1
CLK
CLK
COMMAND ^WRITE
NOP
DQS
tDQSS
2
3
NOP
NOP
4
NOP
5
6
NOP
NOP
7
NOP
8
NOP
DQ's
Din 0 Din 1 Din 2 Din 3 Din 4 Din 5 Din 6 Din 7
DM
masked by DM = H
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
24/50