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M13S32321A_08 Datasheet, PDF (1/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM
ESMT
DDR SDRAM
Features
M13S32321A
256K x 32 Bit x 4 Banks
Double Data Rate SDRAM
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 3; 4
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z VDD = 2.375V ~ 2.625V, VDDQ = 2.375V ~ 2.625V
z Auto & Self refresh
z 32ms refresh period (4K cycle)
z SSTL-2 I/O interface
z 100pin LQFP package
Ordering Information :
PRODUCT NO.
M13S32321A -5L
MAX FREQ
200MHz
VDD
2.5V
M13S32321A -6L
166MHz
2.5V
PACKAGE COMMENTS
100 LQFP
Pb-free
100 LQFP
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
1/50