M13S32321A_08 Datasheet, PDF (17/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins t_DS (Data-in setup time) prior to data strobe edge
enabled after t_DQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
CLK
CLK
2
3
4
COMMAND
NOP
DQS
DQ's
W RITE
NOP
NOP
tDQSS
tDSH
tDSS
tWPRES
NOP
tWPST
Din0 Din1 Din2 Din3
5
NOP
6
NOP
7
NOP
8
NOP
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
17/50