M13S32321A_08 Datasheet, PDF (23/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S32321A
Burst Stop
The burst stop command is initiated by having RAS and CAS high with CS and WE low at the rising edge of the clock
(CLK). The burst stop command has the fewest restriction making it the easiest method to use when terminating a burst read
operation before it has been completed. When the burst stop command is issued during a burst read cycle, the pair of data and
DQS (Data Strobe) go to a high impedance state after a delay which is equal to the CAS latency set in the mode register. The
burst stop command, however, is not supported during a write burst operation.
<Burst Length = 4, CAS Latency = 3 >
0
1
CL K
CL K
COMMAND READ A
B u rs t S t op
2
NOP
3
NOP
4
NOP
5
6
7
8
NOP
NOP
NOP
NOP
CA S Lat en cy= 3
DQS
DQ's
Dout 0 Dout 1
The Burst Stop command is a mandatory feature for DDR SDRAMs. The following functionality is required.
1. The BST command may only be issued on the rising edge of the input clock, CLK.
2. BST is only a valid command during Read burst.
3. BST during a Write burst is undefined and shall not be used.
4. BST applies to all burst lengths.
5. BST is an undefined command during Read with autoprecharge and shall not be used.
6. When terminating a burst Read command, the BST command must be issued L_BST ( “BST Latency”) clock cycles before the
clock edge at which the output buffers are tristated, where L_BST equals the CAS latency for read operations.
7. When the burst terminates, the DQ and DQS pins are tristated.
The BST command is not byte controllable and applies to all bits in the DQ data word and the (all) DQS pin(s).
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
23/50