M13S32321A_08 Datasheet, PDF (34/50 Pages) Elite Semiconductor Memory Technology Inc. – 256K x 32 Bit x 4 Banks Double Data Rate SDRAM

ESMT
Basic Timing (Setup, Hold and Access Time @ BL=4, CL=3)
M13S32321A
Note 1. tHP is lesser of tCL or tCH clock transition collectively when a bank is active.
Elite Semiconductor Memory Technology Inc.
Publication Date : Jul. 2008
Revision : 1.1
34/50