M12S16161A_07 Datasheet, PDF (8/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Mode Register
11 10 9 8 7 6 5 4 3 2 1 0
0 0001
JEDEC Standard Test Set (refresh counter test)
11 10 9 8 7 6 5 4 3 2 1 0
x x 1 0 0 LTMODE
WT
BL
Burst Read and Single Write (for Write
Through Cache)
11 10 9 8 7 6 5 4 3 2 1 0
10
Use in future
11 10 9 8 7 6 5 4 3 2 1 0
x x x 1 1 v v v v v v v Vender Specific
11 10 9 8 7 6 5 4 3 2 1 0
v =Valid
0 0000
LTMODE WT
BL
Mode Register Set
x =Don’t care
Burst length
Bit2-0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
Full page
WT=1
1
2
4
8
R
R
R
R
Wrap type
0
Sequential
1
Interleave
Mode Register Write Timing
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Latency mode
Bits6-4
000
001
010
011
100
101
110
111
CAS Latency
R
R
2
3
R
R
R
R
Remark R : Reserved
Mode Register W rite
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
8/29