M12S16161A_07 Datasheet, PDF (23/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Burst Read Single bit Write Cycle @Burst Length=2
M12S16161A
CLOCK
CKE
*Note1
CS
RAS
CAS
ADDR
BA
A10/AP
RAa
RAa
CL=2
DQ
CL=3
WE
DQM
HIGH
CAa RBb CAb
*Note2
RAc
CBc
CAd
RBb
DAa0
DAa0
RAc
QAb0 QAb1
DBc0
QAb0 QAb1
DBc0
QAd0 QAd1
QAd0 QAd1
Row Active
(A-Bank)
Row Active
(B-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
W rite
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
*Note:1.BRSW modes is enabled by setting A9 “High” at MRS(Mode Register Set).
:Don't Care
At the BRSW Mode, the burst length at write is fixed to “1” regardless of programmed burst length.
2.When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the next cycle of burst-end, so in the case of BRSW write command, the precharge
command will be issued after two clock cycles.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
23/29