M12S16161A_07 Datasheet, PDF (2/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
FUNCTIONAL BLOCK DIAGRAM
M12S16161A
Bank Select
Data Input Register
LWE
LDQM
CLK
ADD
512K x 16
DQi
512K x 16
Column Decoder
LCKE
LRAS LCBR LWE
Latency & Burst Length
Programming Register
LCAS
LWCBR
LDQM
Timing Register
CLK CKE _CS RAS CAS WE L(U)DQM
PIN FUNCTION DESCRIPTION
Pin
CLK
Name
System Clock
CS
Chip Select
CKE
Clock Enable
A0 ~ A10/AP Address
BA
Bank Select Address
RAS
Row Address Strobe
CAS
Column Address Strobe
WE
L(U)DQM
Write Enable
Data Input / Output Mask
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with
CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS , WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
2/29