M12S16161A_07 Datasheet, PDF (6/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter
Symbol
CAS Latency =3
CLK cycle time
tCC
CAS Latency =2
CLK to valid
output delay
CAS Latency =3
tSAC
CAS Latency =2
Output data hold time
tOH
CLK high pulse width
tCH
CLK low pulse width
tCL
Input setup time
tSS
Input hold time
tSH
CLK to output in Low-Z
tSLZ
CLK to output in ^{CAS Latency =3}
Hi-Z
CAS latency =2
tSHZ
-7
Min
Max
7
1000
8.6
-
6
-
6
2
2.5
2.5
2
1
1
-
6
-
6
Unit Note
ns
1
ns
1
ns
2
ns
3
ns
3
ns
3
ns
3
ns
2
ns
*All AC parameters are measured from half to half.
Note: 1.Parameters depend on programmed CAS latency.
2.If clock rising time is longer than 1ns,(tr/2-0.5)ns should be added to the parameter.
3.Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr+ tf)/2-1]ns should be added to the
parameter.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
6/29