M12S16161A_07 Datasheet, PDF (5/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
AC OPERATING TEST CONDITIONS (VDD=2.375~2.625V,TA= 0 to 70 °C )
Parameter
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
M12S16161A
Unit
V
V
ns
V
Ω
Ω
Ω
Ω
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
Row active to row active delay
tRRD(min)
RAS to CAS delay
tRCD(min)
Row precharge time
tRP(min)
Row active time
tRAS(min)
tRAS(max)
Row cycle time
tRC(min)
Last data in to new col. Address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Col. Address to col. Address delay
tCCD(min)
Number of valid output data
CAS latency=3
CAS latency=2
Version
-7
14
20
20
42
100
63
1
2
1
1
2
1
Unit
Note
ns
1
ns
1
ns
1
ns
1
us
ns
1
CLK
2
CLK
2
CLK
2
CLK
3
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
5/29