M12S16161A_07 Datasheet, PDF (19/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Read & Write Cycle with auto Precharge @ Burst Length =4
M12S16161A
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
Ra
BA
A10/AP
Ra
CL=2
DQ
CL=3
WE
Rb Ca
Cb
Rb
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
DQM
Row Active
( A - Bank )
Read with
Auto Precharge
( A - Bank )
Row Active
( B - Bank )
Auto Precharge
Start Point
( A - Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
:Don't Care
*Note: 1.tCDL Should be controlled to meet minimum tRAS before internal precharge start
(In the case of Burst Length=1 & 2 and BRSW mode)
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
19/29