M12S16161A_07 Datasheet, PDF (26/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
Mode Register Set Cycle
CLOCK
0
1
2
3
4
5
6
CKE
HIGH
CS
RAS
CAS
ADDR
DQ
WE
DQM
*Note2
*Note1
*Note3
Key
Ra
Hi-Z
MRS New Command
M12S16161A
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9 10
HIGH
tRC
Hi-Z
Auto Refresh
New Command
:Don't Care
*Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note: 1. CS , RAS , CAS & WE activation at the same clock cycle with address key will set internal mode register.
2.Minimum 2 clock cycles should be met before new RAS activation.
3.Please refer to Mode Register Set table.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
26/29