M12S16161A_07 Datasheet, PDF (20/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
RAS
CAS
ADDR
Ra
BA
A10/AP
Ra
DQ
WE
DQM
Ca
Cb
Cc
Qa0 Qa1
Qa2
Qa3
tSHZ
Qb0
Qb1
tSHZ
Dc0
Dc2
*Note1
Row Active
Read
Clock
Suspension
Read
Read DQM
Write
DQM
Write
Clock
Suspension
Write
DQM
*Note:1.DQM is needed to prevent bus contention.
:Don't Care
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
20/29