M12S16161A_07 Datasheet, PDF (22/29 Pages) Elite Semiconductor Memory Technology Inc. – 512K x 16Bit x 2Banks Synchronous DRAM

ESMT
M12S16161A
Write Interrupted by Precharge Command & Write Burst stop Cycle @ Burst Length =Full page
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18 19
CLOCK
CKE
HIGH
CS
RAS
CAS
ADDR
BA
A10/AP
RAa
RAa
DQ
WE
DQM
CAa
CAb
tBDL
DAa0 DAa1 DAa2 DAa3 DAa4
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
tRDL
*Note2
Row Active
( A- B an k )
W rite
(A-Bank)
Burst Stop
W rite
(A-Bank)
Precharge
( A- B an k )
:Don't Care
*Note: 1. Burst can’t end in full page mode, so auto precharge can’t issue.
2.Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by
AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
Input data after Row precharge cycle will be masked internally.
3.Burst stop is valid at every burst length.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2007
Revision : 1.1
22/29